Parallel buses, such as data bus, address bus, control bus, and the like, can be used to transmit multiple bits in parallel. Generally, it can be preferred that the multiple bits can be synchronized with substantially equal delays at various connector levels, such as integrated circuit pads, printed circuit board (PCB) connectors, and the like. In a technique to synchronize the delays of the multiple bits, layout engineers may route the multiple bits based on simulation reports. The simulation based technique may increase time to market, and may introduce errors, for example, due to lack of accuracy of models used in the simulation.